Asynchronous CPU

For a full implementation of these gates, please visit our download page.

One major disadvantage in an asynchronous design is the amount of hardware overhead required to prevent glitching. Everything, down to the most basic gates, requires a start and finish signal to regulate when each process may operate. To give an idea of what this might entail, we include a set of basic gates, composed of typical logic gates, that would include this feature.

We first construct a "Realistic gate" by giving each logic gate a propogation delay. The figure shown below is that of an AND gate. The structure are the same for AND, OR, and XOR gates

Our preliminary asynchronous structure is shown first. Here, we went by the logic that a finish signal will only flag up if the output true or false signal is flagged. This only happens if the start signal is on, requiring start to be on for the process to run.

After further inspection, however, we realized that this method didn't take into account the propogation delay in the leftmost few logic gates, as that may cause glitching. We therefore designed an even more complicated logic gate implemtation, in which no operation is initiated until the input signals are ready, and each enable is wired to the ready signal of the previous step. A typical two-input logic gate would therefore look as follows.

A signal-input logic gate, such as a NOT operation, would look as such:

We did test for all the gates. An example of the test for the asnychronous XOR and asynchronous NOT are shown below. The signals, from top to bottom, are: Input A, input B, start, XOR output, and NOT output (with A as input).

The results shown above are as expected. For example, in the first segment, from 0-100 time unit, the inputs and start are all 1, so the output is 0 for XOR and NOT and 1 for done. While the start and done signals look simutaneous, done have a very tiny lag, which is apparent in the major components, which requires a large amount of gates and contains more delay.

Although we have not fully vetted this structure, we believe it will be immune to glitching. This is a rather depressing thought, as a two-input gate is now composed of 14 logic gates, and a one-input gate is composed of 7 logic gates. Considering that our typical CPU design is composed almost solely of logic gates, this sort of expansion would result in an order of magnitude increase in hardware overhead. However, hope is not to be lost completely. First, as the transistor is now shrinking to unbelievable sizes, the actual area overhead may not even be that noticeable. In addition, not all of the CPU needs to be asynchronous; on some level, there may be localized clocks, implementing start-finish flags on a much larger scale than at the gate level. And finally, if it does turn out that the hardware overhead is too much to bear, a paradigm shift may be in order. Although we naturally think in logic gates, it may be better to redesign our way of thinking. Since asynchronous design is more suited for parallel processing than sequential anyways, this may be the perfect opportunity to switch to that mindset in order to produce a more optimal CPU.