Asynchronous CPU

In order to model the hardware environment, our implementation was done entirely in Mathworks's Simulink, a high-level modeling tool. The simulations were done entirely using Euler to correctly model causality, using a step size of 0.1 seconds.

The advantages of simulink is in its flexibility for abstraction. This allowed us to simplify the complexity of the CPU by creating MatLab Embedded structures for things like muxes, ALUs, and registers; these structures could then be constructed seperately. Also, because Simulink is a visual programming tool and allowes for easy creation of subsystems, it allowed us to easily envision how each module fit into the picture.

The one major disadvantage of using simulink, however, is the inability to create one subsystem, stick it in a library, and have every subsequent use of that subsystem be sourced to one particular file. This created a lot of headache for us, as any modification to one particular element resulted in the need to modify this element in every copy of that element. This is especially irritating when we have structures like 32 by 32 bit registers, each needing a decoder; for this reason, although we did create an ALU, mux, register, and CPU, we never combined them together into one fully-asynchronous completely hardware-defined asynchronous CPU.

Our work should therefore not be viewed as an implementation of an asynchronous CPU, but a fully vetted blue-print of what should work. If anyone wishes to take on this project in the future, it would be advised to simulate this in an environment more like Verilog, as the pictures are literally already drawn out.